1. Field of the Invention
This invention relates to apparatus for detecting and recovering binary data from an input signal and more particularly to deriving a synchronized clock from an input signal which is received intermittently in the presence of noise and for inhibiting the output of detected binary data as a function of the noise to eliminate false or unreliable data.
2. Description of the Prior Art
Binary data may be sent to an aircraft in the form of a radio signal at a fixed frequency with phase modulation. One example of phased modulation is differentially phase shift keyed (DPSK) modulation. In DPSK modulation, the data is encoded prior to transmission and is decoded upon reception by comparing two successive encoded data bits. Each encoded data bit has a predetermined time interval and has a phase relationship depended upon whether a one or zero is represented.
In order to recover the binary data from an encoded DPSK data stream, a synchronized clock must be generated from the received signal if not independently available. Obtaining a synchronized clock may be difficult in an aircraft environment where the distance from the source of radio signals may result in a low signal level compared to other received signals. Furthermore, erroneous data will be decoded if an unsynchronized clock is inadvertently generated such as from noise or interferring signals or where a synchronized clock continues to decode apparent data after the data transmission has terminated.
An alternative approach for decoding DPSk data is by using a large shift register with a high speed nonsynchronized clock. This approach is costly in terms of hardware to implement.
It is therefore desirable to provide a circuit for recovering binary data from an input signal by generating a synchronized clock from the input signal by sensing the transitions between ones and zeros of the transmitted data and resetting a counter in response to detected transitions and having its output used to reset a second counter wherein the output of the second counter is synchronized with the binary data.
It is further desirable to provide a synchronous clock from the input signal that will continue after the input signal has terminated for at least one data time interval.
It is further desirable to provide a squelch circuit for inhibiting the decoded binary data as a function of the noise on the input signal.
It is further desirable to provide a squelch circuit for inhibiting the apparent decoded data at times when no data is in fact being received by detecting the output of the intermediate frequency amplifier of a receiver after hard limiting.